Integrated circuit (IC) chips or dice are commonly packaged before assembly on a printed wiring board (PWB). The package has several important functions, including interconnection (power and signal transmission), mechanical and environmental protection, and heat dissipation. In addition, the package acts as a mechanism for “spreading apart” the connections from the tight pitch (center to center spacing between bond pads) on the IC chip to the relatively wide pitch required by the printed circuit board manufacturer.
In the highly competitive market of electronic packaging, factors of performance, throughput, cost, and reliability have a major influence on packaging technologies. Although packaging is usually performed on individual IC chips, there is growing interest in developing methods of packaging ICs at the wafer level, (i.e., before singulation of individual chips from the wafer). Wafer-level packaging can potentially achieve higher throughput, higher reliability, and lower costs than individual chip packaging.
The reliability of IC packages is often limited by failure of the interconnect elements (e.g., solder joints, bond wires) between the die and the package substrate or between the package and the PWB. Such failures are often due to mechanical stresses incurred during package assembly and/or differences in coefficients of thermal expansion (CTE) between the silicon die and substrate materials. Consequently, various approaches to minimizing mechanically or thermally induced stresses in semiconductor packages have been reported. For example, U.S. Pat. No. 5,171,716 to Cagan et al. discloses a semiconductor device containing a stress-relief layer having a glass transition temperature below 150° C.
Kang et al. teach a wafer-level chip scale package containing a high CTE/modulus dielectric polymer as a stress buffer layer (Electronic Components and Technology Conference Proceedings, 2000, 87-92).
Strandjord et al. teach a one mask process for stress-buffer and passivation applications using photosensitive benzocyclobutene (IEMT/IMC Symposium Proceedings, 1997, 261-266).
U.S. Pat. No. 6,103,552 to Lin discloses a process and a package for wafer-scale packaging. The process includes depositing a layer of a polymeric material, such as polyimide, silicone elastomer, or benzocyclobutene on the surface of a chip. The '552 patent further teaches that the temperature coefficient of expansion of the polymer should be low so as to match that of the metal studs in the package, thereby minimizing local stresses at the stud-polymer interface.
U.S. Pat. No. 6,197,613 to Kung et al. discloses a method of forming a wafer-level package wherein an insulative elastic material layer is provided as a base layer for a multiplicity of metal traces wherein the elastic material has a sufficiently low Young's modulus for functioning as a stress-buffing layer.
U.S. Pat. No. 6,277,669 to Kung et al. discloses a method for fabricating a wafer-level package wherein an elastomeric material layer is first deposited on top of a passivation layer by a printing, coating or laminating method to form a plurality of isolated islands.
Although the aforementioned approaches to semiconductor packaging provide packages having a range of thermal properties, there is a continued need for a semiconductor package having superior thermal stability and reliability.